This invention relates to a semiconductor integrated circuit device. More particularly, it relates to a technique which is effective when utilized for a semiconductor integrated circuit device, for example, a dynamic RAM that has a booster circuit for forming a timing signal having a high level above a power source potential.
In a semiconductor integrated circuit device such as a dynamic RAM which employs one-MOSFET type memory cells each being constructed of a storage capacitor and an address selecting MOSFET, a booster circuit (bootstrap circuit) is typically provided by which the selective level of a word line coupled to the gate of the address selecting MOSFET is raised to a potential higher than a power source potential. The reason that such a booster circuit is provided is that the gate (word line) level of the address selecting MOSFET in the memory cell is rendered higher than the power source potential thus, a high level for writing or rewriting information into the storage capacitor is prevented from lowering due to the threshold voltage of the MOSFET. In addition, in reading out information from the memory cell, a signal is transmitted to a data line fast and efficiently.
As such booster circuits, there have been proposed various booster circuits of, for example, the direct bootstrap system described in IEEE Journal of Solid-State Circuits, Vol. SC-16, No. 5, pp. 492-497.